Thanks so much for posting this!
I was asked to add this functionality to my Android app “Code Peeker” and this was exactly what I needed.
https://market.android.com/details?id=twig.nguyen.codepeeker

I have never heard of verilog before but the person requesting it gave me a list of keywords.

I’ve added the entries missing from your keywords list, a whole 127 of them!

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‘alias always always_comb always_ff always_latch and assert assume automatic before bind bins binsof bit break byte cell chandle class clocking config const constraint context continue cover covergroup coverpoint cross design dist do end endcase endclass endclocking endconfig endgenerate endgroup endinterface endpackage endprogram endproperty endsequence enum expect export extends extern final first_match foreach fork forkjoin generate genvar iff ifnone ignore_bins illegal_bins import incdir inside instance int interface intersect join_any join_none liblist library local localparam logic longint matches modport new noshowcancelled null or package packed priority program property protected pulsestyle_onevent pulsestyle_ondetect pure rand randc randcase randsequence ref return rpmos sequence shortint shortreal showcancelled signed solve static string struct super tagged this throughout timeprecision timeunit tranif1 type typedef union unique unsigned use var virtual void wait_order wildcard with within xorA’;