Posted by Hanly on Oct 18, 2010 in Blog, Code, Sample Work | 0 comments
Behavioral Verilog is the most abstract style of Verilog code. The code looks very similar to C, but one has to remember that in hardware operations occur in parallel, and everything is running at once.
This sample register file will be a 16 entries by 8-bits per entry. It will have 2 synchronous write ports, and an asynchronous read port as well as an active low asynchronous reset.
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Posted by Hanly on Oct 16, 2010 in Blog, Code | 5 comments
Yesterday I had to complete a programming exercise as part of a research internship I will be starting Nov. 2nd. I had to create a simple C++ program which would take the mean, median, and mode of a set of numbers of unknown length. I was free to implement it any which way, with the exception of using arithmetic libraries to do my mean, median, and mode computations.
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